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The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.

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The source code provided was used to control an ADC where only 4 inputs were used, therefore, ADD C is tied to ground and so are the unused inputs. A, B, and C.

You will also need to download multiplex. Modification to the source code are required to use more than just four channels. At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins. Clock The clock signal is required to cycle through the xdc0809 stages to do the conversion. This is an address select line for the multiplexer.

The maximum frequence of the clock is 1. This means that in order to get it to work, there is a total of seven control signals that dataeheet be sent from the FPGA. There are a couple of limitations that follow: The voltage level that, when received as an input, will output “” to the FPGA.

Table 2 provides a summary of all of the input and output to the chip. This is a bit of the digital converted output. The signal goes low once a conversion is initiated by the start signal and remains low until a conversion is complete.


National Semiconductor

The minimum pulse width is ns. Be sure to consult the manufactures data-sheets for other chips. It is the LSB of the select lines. It goes low when a conversion is started and high at the end of a conversion. The ALE should be pulsed for at least ns in order for the addresses to get loaded properly. All of the signals are explained below.

See adc08809 1 for details.

This means it must remain stable for up to 72 clock cycles. On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated. The signal datahseet be tie to the ALE signal when the clock frequency is below kHz. It is the Second bit of the select lines. Users can look for a rising edge transition.

ADC Technical Data

The source resistance must be below 10kohms for datashfet below kHz and below 5kohms for operation around 1. It is the MSB of the select lines. Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals. In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA. If Vcc and ground are used as reference voltages, they should be isolated by decoupling with a 1 microF capacitor.

Top rail of Reference voltage.

This means that an entire adc009 takes at least 64 clock cycles. There adc809 8, 8 clock cycle periods required in order to complete an entire conversion.

Control signal from FPGA. The OE signal should conform to the same range as datsaheet the other control signals. As with all control signals it is required to have an input value of Vcc – 1.


The following control signals are used to control the conversion. All control signals should have a high voltage from Vcc – 1. The other files are enabled register, a register, and a multiplexer. The source must remain stable while it is being sampled and should contain little noise. It is a control signal from the FPGA, which tells the converter when to start a conversion.

Source code The source code consists of a few of files. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled. Once loaded the multiplexer sends the appropriate channel to the converter on the chip.

It is recomended that the source resistance catasheet exceed 5kohms for operation at 1. For a quick reference refer to table 2. Note that it can take up to 2.

The maximum clock frequency is affected by the source impedance of the analog inputs. The clock should conform to the same range as all other control signals. It can be tied to the Start line if the clock is operated under kHz.

Analog to Digital Converter – ADC/ADC

Like the ALE pulse the minimum pulse width is ns. Up to 72 if the start signal is received in the middle of an 8 clock cycle period. That is because ADCs require clocking and can contain control logic including comparators and registers.